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UCB1510 ac97 digital modem codec rev. 01 4 february 2000 preliminary speci?cation c c 1. description the UCB1510 is a single chip, integrated mixed signal telecom codec that can directly be connected to a daa and supports high speed modem protocols. the general purpose i/o pins provide programmable inputs and/or outputs to the system. the UCB1510 has a serial aclink interface intended to communicate to the system controller. both the codec input data and codec output data and the control register data are multiplexed on this interface. 2. features n sigma delta telecom codec with programmable sample rate, including digitally controlled input voltage level, mute, loop back and clip detection functions. the telecom codec can be directly connected to a data access arrangement (daa) and includes a built in sidetone suppression circuit n aclink (rev 2.1) interface with secondary codec support n 3.3 v supply voltage and built in power saving modes make the UCB1510 optimal for portable and battery powered applications n 5 v tolerant interface for motherboard/pc add on n maximum operating current 25 ma n 8 general purpose io pins for line interface control n interrupt detection driven wake up sequence for ring detect n low cost 12.288 mhz crystal 3. applications n standalone modems n integrated modems n audio/modem riser (amr) cards n mobile daughter cards (mdc)
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 2 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 4. ordering information 5. block diagram table 1: ordering information type number package name description version UCB1510db ssop28 plastic shrink small outline package, 28 leads, body width 5.3mm sot341-1 fig 1. block diagram adc dac down sample filter up sample filter gpio data / control registers voltage reference serial bus interface clock buffers & sample rate dividers tinp tinn toutp toutn io[7:0] sdout sdin sync reset bit_clk xtal_in/ a1 vrefbyp line1 pcm flow xtal_out pon a0
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 3 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration UCB1510 vssa tinn tinp vrefbyp toutn toutp vdda vssd io7 io6 io5 io4 io0 io1 io2 io3 reset a0 vddd pon sync sdout vssd sdin bit_clk vddd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 25 24 23 22 21 20 19 18 17 16 xtal_out xtal_in/ a1 28 27 table 2: pin description symbol pin reset state [1] type [2] description v ddd 1 - s digital supply io0 2 input i/o c general purpose i/o pins io1 3 input i/o c general purpose i/o pins io2 4 input i/o c general purpose i/o pins io3 5 input i/o c general purpose i/o pins reset 6 - i c asynchronous reset input a0 7 - i c address select (for secondary codec) - inverted polarity pon 8 - i c asynchronous cold reset sync 9 - i/o c aclink synchronization input sdout 10 - i c aclink data input v ssd 11 - s digital ground sdin 12 0 [4] o c aclink data output bit_clk 13 - [3] i/o c aclink serial interface clock v ddd 14 - s digital supply io4 15 input i/o c general purpose i/o pins
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 4 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. [1] after cold or warm reset, the aclink interface is active with mlnk bit reset. [2] i/o c = cmos bidirectional; i d = digital input; s = supply; o a = analog output; i c = cmos input; i a = analog input; i/o a = analog bidirectional; o c = cmos output. [3] bit_clk is an input for aclink secondary codec, an output for primary codec. when bit_clk is an output, the xtal oscillator is active. [4] sdin is driving a 0 until a valid sync framing signal is received after cold reset. io5 16 input i/o c general purpose i/o pins io6 17 input i/o c general purpose i/o pins io7 18 input i/o c general purpose i/o pins v ssd 19 - s digital ground v dda 20 - s analog supply toutp 21 hi z o a positive telecom codec output toutn 22 hi z o a negative telecom codec output vrefbyp 23 hi z i/o a external reference voltage bypass tinp 24 - i a positive telecom codec input tinn 25 - i a negative telecom codec input v ssa 26 - s analog ground xtal_in/ a1 27 - [3] i a /i c xtal oscillator/master clock input or inverted secondary address xtal_out 28 - [3] o a xtal oscillator output table 2: pin description continued symbol pin reset state [1] type [2] description
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 5 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 7. functional description the functional description of the devices id described in section 8 through section 15 . 8. telecom codec the telecom codec contains an input channel, built up from a 64 times oversampling sigma delta analog to digital converter (adc) with digital decimation ?lters, programmable gain and attenuation and built-in sidetone suppression circuit. the output path consists of a digital up sample ?lter, a 64 time oversampling 4 bit digital to analog converter (dac) circuit with integrated ?lter followed by a differential output driver, capable of directly driving a 600 w isolation transformer. the output path includes a mute function. the telecom codec also incorporates loop back modes, in which codec output path and the input path are connected in series. the loop back tap and entry points are identi?ed as circled letters in figure 3 , loop back modes are described in the aclink register de?nition. the telecom sample rate (f st ) is derived from the ac master clock and is programmable using the sample rate registers. not all ac97 speci?ed sample rates are supported, refer to table 3 sampling frequencies for details. pcm data is transferred in the slot 5 of the aclink. fig 3. telecom codec block diagram tinp toutp toutn sidetone_enable adc digital decimation filter 14 14 dac mute dac digital noise shaper tinn sidetone suppression circuit adc[3:2] e c j h g b d
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 6 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. any programmed vlaue above 24 khz will lead to a 24 khz sampling rate. changing the sampling rate while the codec is active may lead to unpredictable results in the adc and dac chains and should be avoided. the output section of the telecom codec is designed to interface with a 600 w line through an isolation transformer. the built in mute function is activated by the dac mute bit in register 0x46. the output driver remains active in the mute mode, however no output signal is produced. 8.1 digital ?lters these ?lters are tailored for high speed modem performance. a voice band ?lter can be activated to reduce the noise in the lower frequencies. table 3: sampling frequencies sampling frequency (hz) register 0x40 value support ac 97 requirements 7200 0x1c20 no recommended 8000 0x1f40 yes required 8228.57 (57600/7) 0x2024 no recommended 8400 0x20d0 no recommended 9000 0x2328 no recommended 9600 0x2580 yes required 10285.71 (72000/7) 0x282d no recommended 12000 0x2ee0 yes recommended 13714.29 (96000/7) 0x3592 yes required 16000 0x3e80 yes required 19200 0x4b00 yes recommended 24000 0x5dc0 yes recommended 48000 0xbb80 no recommended table 4: filter characteristics parameter condition value group delay 25 samples pass band ripple 0.1 db out of band rejection >0.55 fs -50 db pass band (no voice band ?lter) 0.0016 to 0.45 fs transition band 0.45 to 0.55 fs voice band ?lter rejection band 0-0.0018 fs 30 db voice band ?lter cutoff frequency 0.05 fs
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 7 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 8.2 analog interface an important built-in feature of the telecom codec is the sidetone suppression circuit. the sidetone suppression circuit is activated when sidetone_enable of register 0x5a is set.the sidetone suppression circuit subtracts part of the telecom output signal from the telecom input signal. as a result the available dynamic range of the input path can be more effectively utilized. if the sidetone suppression circuit is disabled, the telecom input dynamic range can be largely occupied by the telecom output signal. the built-in side tone suppression circuit, shown in figure 4 , has a ?xed subtraction ratio, set be the resistors r s and r i , which equals 600 456 . this ratio is calculated from the following relations. the impedance seen by the telephone line equals: , differential, in which r t represents winding resistance of the transformer, divided by 2. assuming r i >> r o , then single ended. a typical transformer has 156 w winding impedance, thus r o should be 144 w . the ratio of the telecom input and output voltage is, therefore: proper sidetone suppression thus requires r s /r i to be v i /v o . fig 4. typical telecom codec sidetone suppression circuit (without protection circuits). - + rs toutp tinp ri rg ro rt - + rs toutn tinn ri rg ro rt rt rt 1:1 transformer a b UCB1510 central office z line 2r t r t r o r i r o r i + ----------------- - ++ ? ?? = r line r t r t r o 600 2 300 w == ++ = v i(tel) v o(tel) 156 300 + 156 300 144 ++ --------------------------------------- v o(tel) 456 600 -------- - = =
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 8 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 9. on-chip reference circuit the UCB1510 contains an on chip reference voltage source, which generates the bias currents and the virtual analog ground. alternatively the UCB1510 can be driven from an external reference voltage source. two bits in the control register 0x5a determine the mode of operation of this reference voltage circuit. vref_bypass connects the internal reference voltage to the vrefbyp pin, while vref_external disables the internal reference voltage and switches the UCB1510 into the external voltage reference mode. if the internal reference voltage is connected to the vrefbyp pin, an external capacitor could be connected to ?lter this reference voltage. when choosing a capacitor, the internal impedance (around 50 k w ) should be taken into account. if vref_external is set, an external voltage reference connected to the vrefbyp pin is used as the voltage reference by UCB1510. 10. power supply strategy since all the control logic of the UCB1510 is powered by the v ddd , power should always be present on this pin for interrupts to be possible. v dda needs not be present all the time although it is recommended to use the control bits to turn off the analog sections. fig 5. block diagram of the reference circuit. & & vref_external internal bandgap reference voltage circuitry ena vbg vref_bypass internal analog ground vrefbyp bias ena
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 9 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11. register de?nition 11.1 supported registers 11.2 register detail shaded areas indicate read only data. 11.2.1 extended modem id [1] writing this register will cause a register reset: all modem registers will then take their default values. table 5: supported registers register name 0x00 to 0x3a all audio registers are ignored 0x3c extended modem id 0x3e extended modem status and control 0x40 line1 dac/adc rate 0x42 and 0x44 reserved for future use 0x46 line1 dac/adc level 0x48 and 0x4a reserved for future use 0x4c gpio pin con?guration 0x4e gpio pin polarity 0x50 gpio pin sticky 0x52 gpio pin wake-up mask 0x54 gpio pin status 0x56 miscellaneous modem afe status and control 0x58 ignored 0x5a codec control 0x5c mode control 0x5e test control 0x5e to 0x7a ignored 0x7c vendor id1 0x7e vendor id2 table 6: extended modem id register register address: 0x3c; default: n/a bit d15 d14 d13 d12 d11 d10 d9 d8 symbol id1 id0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 0 0 0 lin1 table 7: description of extended modem id bits bit symbol function/value d15:14 id[1:0] {a1,a0} where a0 is the inverse polarity of the a0 pin. a1 is the inverse polarity of xtal_in pin if a0 is high ( a0 pin is low), otherwise a1 is 0. d0 lin1 line 1 support indicator = 1 (i.e., line 1 is supported).
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 10 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11.2.2 extended modem status and control 11.2.3 line 1 sample rate refer to table 3 sampling frequencies for supported sample rates. table 8: extended modem status and control register register address: 0x3e; default: 0xffxx bit d15 d14 d13 d12 d11 d10 d9 d8 symbol prh prg prf pre prd prc prb pra bit d7 d6 d5 d4 d3 d2 d1 d0 symbol hdac hadc dac2 adc2 dac1 adc1 mref gpio table 9: description of extended modem status and control bits bit symbol function/value d15 prh reserved, should be 1 d14 prg reserved, should be 1 d13 prf reserved, should be 1 d12 pre reserved, should be 1 d11 prd 1 -> line1 dac off d10 prc 1 -> line1 adc off d9 prb 1 -> line1 v ref off d8 pra 1 -> gpio off d7 hdac 0 (not supported) d6 hadc 0 (not supported) d5 dac2 0 (not supported) d4 adc2 0 (not supported) d3 dac1 1 indicates line1 dac ready (means that the line1 dac and the v ref are enabled and ready) d2 adc1 1 indicates line1 adc ready (means that the line1 adc and the v ref are enabled and ready) d1 mref 1 indicates line1 v ref up to nominal level. d0 gpio 1 indicates gpio ready. table 10: line 1 sample rate register register address: 0x40; default: 0x1f40 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 11 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11.2.4 line 1 dac/adc level 11.2.5 gpio pin con?guration the gpio pin con?guration register speci?es whether a gpio pin is con?gured for input (1) or for output (0). 11.2.6 gpio pin polarity the gpio pin polarity register de?nes gpio input polarity (0 = low, 1 = high) when a gpio pin is con?gured as an input. table 11: line 1 dac/adc level register register address: 0x46; default: 0x8080 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol dac mute bit d7 d6 d5 d4 d3 d2 d1 d0 symbol adc mute adc3 adc2 adc1 adc0 table 12: description of line1 dac/adc level bits bit symbol function/value d15 dac mute dac section is active, but no signal will be sent. d7 adc mute adc section is active, but no signal will be sent. d3-d2 adc[3:2] adc gain (0 -> 0 db, 1 -> 6 db, 2 -> 12 db, 3 -> 18 db) d1-d0 adc[1:0] these bits are ignored. table 13: gpio pin con?guration register register address: 0x4c; default: 0x00ff bit d15 d14 d13 d12 d11 d10 d9 d8 symbol bit d7 d6 d5 d4 d3 d2 d1 d0 symbol gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 table 14: gpio pin polarity register register address: 0x4e; default: 0xffff bit d15 d14 d13 d12 d11 d10 d9 d8 symbol bit d7 d6 d5 d4 d3 d2 d1 d0 symbol gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 12 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11.2.7 gpio pin sticky the gpio pin sticky register de?nes gpio input type (0 = non-sticky, 1 = sticky) when a gpio pin is con?gured as input. sticky is de?ned as edge sensitive, non-sticky as level-sensitive. gpio inputs con?gured as sticky are cleared by writing a 0 to the corresponding bit of the gpio pin status register 0x54, and by reset. remark: changing gpio control registers while a gpio is sticky may cause unwanted interrupts and should be done carefully. 11.2.8 gpio wake-up mask the gpio pin wake-up mask register provides a mask for determining if an input gpio change will generate a wake-up or gpio_int (0 = no, 1 = yes). when the ac-link is powered down, a wake-up event will trigger the assertion of sdin. when the ac-link is powered up, a wake-up event will appear as gpio_int = 1 on bit 0 of input slot 12. 11.2.9 gpio pin status the gpio status register re?ects the state of all gpio pins (inputs and outputs) on slot 12. when the gpio is an output pin, the value set on slot #12 is transmitted directly to the pin. when the gpio pin is a non-sticky input, the status of the pin is accessible in read mode. when the gpio is a sticky input, a transition, either from high to low (polarity = 0) or from low-to-high (polarity = 1), will assert the corresponding gi bit to 1. the gi bit will remain asserted until it is cleared by a write of 0. table 15: gpio pin sticky register register address: 0x50; default: 0x0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol bit d7 d6 d5 d4 d3 d2 d1 d0 symbol gs7 gs6 gs5 gs4 gs3 gs2 gs1 gs0 table 16: gpio wake-up mask register register address: 0x52; default: 0x0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol bit d7 d6 d5 d4 d3 d2 d1 d0 symbol gw7 gw6 gw5 gw4 gw3 gw2 gw1 gw0 table 17: gpio pin status register register address: 0x54; default: n/a bit d15 d14 d13 d12 d11 d10 d9 d8 symbol bit d7 d6 d5 d4 d3 d2 d1 d0 symbol gi7 gi6 gi5 gi4 gi3 gi2 gi1 gi0
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 13 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11.2.10 miscellaneous modem afe status and control table 18: miscellaneous modem afe status and control register register address: 0x56; default: 0x0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol mlnk reserved, should be 0x0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol reserved, should be 0x0 l1b2 l1b1 l1b0 table 19: description of miscellaneous modem afe status and control bits bit symbol function/value d13 mlnk 1 -> aclink goes to sleep. d[2:0] l1b[2:0] line1 loop back modes (refer to ta b l e 2 0 ). table 20: loop back modes see figure 3 . mode description 0 disabled 1 adc loop back (incoming analog signal is ampli?ed, digitized, down-sampled, looped, up-sampled, converted to analog, ampli?ed/?ltered) (g) to (b) loop. 2 local analog loop back (digital signal is up-sampled, converted to analog, ampli?ed/?ltered, looped, ampli?ed, digitized, down-sampled, sent back) (e) to (j) loop. 3 dac loop back (digital signal is up-sampled, converted to analog, looped digitized, down-sampled, sent back) (e) to (j) loop. same as mode 2. 4 remote analog loop back (incoming analog signal is ampli?ed, looped, ampli?ed/?ltered, sent back) (j) to (d) loop. 7 digital loop back: signal is captured from the ac-link and sent back as is. slot request for slot#5 is controlled according to the programmed sampling rate.
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 14 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11.2.11 vendor speci?c codec control 11.2.12 vendor speci?c mode control [1] bits marked 0 are reserved for future use and should be programmed with 0. 11.2.13 vendor speci?c test control this register cannot be reset. it has no effect until the ic is put in vendor test mode (see table 29 mode selection with ac pins ). table 21: codec_control register register address: 0x5a; default: 0x0400 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol ac me ve vb bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 0 0se0 0 0vf table 22: codec_control bits bit symbol function/value d12 ac adc_clip, in read mode, this bit indicates clipping in the line1 adc. this indicator is sticky and should be cleared by writing it with a 0. d10 me reserved, should be 1 d9 ve vref_external, overwrites vb d8 vb vref_bypass d[7:5], d[3:1] 0 bits marked 0 are reserved for future use and should be programmed with 0. d4 se sidetone_enable d0 vf voice_?lter:1->enable voice band digital ?lter. table 23: mode_control register register address: 0x5c; default: 0x0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol reserved: 0x0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 0 0 0 bitstream table 24: mode_control bits bit symbol function/value d0 bitstream line1 adc bitstream data is sent directly to io4. the associated clock is sent to io6. table 25: test_control register register address: 0x5e; default: n/a bit d15 d14 d13 d12 d11 d10 d9 d8 symbol bit d7 d6 d5 d4 d3 d2 d1 d0 symbol
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 15 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 11.2.14 vendor id1 11.2.15 vendor id2 11.3 register reset modes 11.3.1 warm reset when a warm reset is activated, mlnk is set to 0 but the other registers retain their values. if the codec is primary, the bit_clk is started and stabilized after 200 ms. 11.3.2 cold reset when a cold reset is activated, mlnk is set to 0 and all registers are programmed to their default values. if the codec is primary, the bit_clk is started and stabilized after 200 ms. 11.3.3 register reset a register reset causes all registers to return to their default values. initiated by a write to register 0x3c. table 26: vendor id1 register register address: 0x7c; default: 0x5053 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol 0 1 0 1 0 0 0 0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 1 0 1 0 0 1 1 table 27: vendor id2 register register address: 0x7e; default: 0x4301 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol 0 1 0 0 0 0 1 1 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 0 0 0 0 0 0 1
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 16 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 12. ac97 interface 12.1 control register data transfer the aclink frames is made of 13 slots. slot0 is a 16-bit long tag slot, the remaining 12 slots are 20-bit long data transfer. register update is done at the end of slot 2. the new register value is effective thereafter. slot #0 and slot #3 to #12 are shared by all codecs (primary and secondary). multiple codecs using the same slot cannot be used at the same time. slot #1 and slot #2 are used for register transfer and are codec speci?c. addressing is de?ned in the tag slot #0: the UCB1510 will send a 1 as tag slot bit 15 whenever the aclink is active (mlnk is 0). fig 6. aclink frame slot de?nition sync sdout (slot #) slot #0: tag slot #2: cmd data slot #1: cmd addr slot #3 & #4: slot #6.. #9: slot #5: line1 dac slot #12: i/o ctrl not supported by UCB1510 not supported by UCB1510 48khz 16 bits #0 #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #0 20bits clock:12.288mhz
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 17 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. fig 7. tag slot bit de?nition (controller to codec) 1514131211109876 543210 19 18 17 16 15 16 bit_clks 0 sync bit_clk slot #0 slot #1 sdout (bit numbers) bit 15: if 1 then valid frame; if 0 then frame can be ignored bit 14: if 1 then slot #1 (cmd_addr) is valid bit 13: if 1 then slot #2 (cmd_data) is valid bit 12: if 1 then slot #3 is valid - should be 0 for UCB1510 bit 11: if 1 then slot #4 is valid - should be 0 for UCB1510 bit 10: if 1 then slot #5 (line 1) is valid bit 9: if 1 then slot #6 is valid - should be 0 for UCB1510 bit 8: if 1 then slot #7 is valid - should be 0 for UCB1510 bit7: if 1 then slot #8 is valid - should be 0 for UCB1510 bit 6: if 1 then slot #9 is valid - should be 0 for UCB1510 bit 5: if 1 then slot #10 is valid - should be 0 for UCB1510 bit 4: if 1 then slot #11 s valid - should be 0 for UCB1510 bit3: if 1 then slot #12 (i/o control) is valid bit 2: unused, set to 0 bit 1: codec id a1 bit 0: codec id a0 bit 19: read/write (1-> read) bit 18: register index[6] bit 16: register index[4] bit 15: register index[3] bit 17: register index[5] fig 8. tag slot bit de?nition (codec to controller) 1514131211109876 543210 19 18 17 16 15 16 bit_clks 0 sync bit_clk slot #0 slot #1 sdin (bit numbers) bit 15: if 1 then valid frame; if 0 then frame can be ignored bit 14: if 1 then slot #1 (cmd_addr) is valid bit 13: if 1 then slot #2 (cmd_data) is valid bit 12: 0 bit 11: 0 bit 10: if 1 then slot #5 is valid bit 9: 0 bit 8: 0 bit7: i0 bit 6: 0 bit 5: 0 bit 4: 0 bit3: if 1 then slot #12 (i/o control) is valid bit 2: unused, set to 0 bit 1: 0 bit 0: 0 bit 19: register_read bit 18: register index[6] bit 16: register index[4] bit 15: register index[3] bit 17: register index[5]
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 18 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 12.2 codec addressing 12.2.1 primary codec addressing for addressing a primary codec, bits 1 and 0 of the tag slot (codec id a1 and a0) should be 0. the bits 13 and 14 are used for register data transfer. when the controller is not sending/receiving control data, it should be addressing the primary codec. when writing to a register, the bits 14 and 13 (addr and data valid) should be set to 1. when reading from a register, only the bit 14 is required to be 1. 12.2.2 secondary codec addressing when the codec id (a1,a0) is not 00, the controller is addressing a secondary codec in a read or write sequence. the direction is de?ned in the slot 1 read/write bit (bit 19). 12.3 pcm sample transfer since the aclink frame frequency is de?ned to be 48khz, exchanging samples with the controller at a different sampling rate requires the support of on demand sample transfer (slot request). the UCB1510 will send samples to the controller and assert the slot 5 valid bit in the slot#0 (bit10)of the aclink frame. when it needs a new sample from the controller, it will put a 0 on the slot5req bit in the slot#1 (bit9) of the aclink frame. when the slot5req bit is 1, it indicates to the controller that no new sample is needed. when the dac is not active, the slot5req bit is kept at 0. table 28: codec addressing examples cmd addr cmd data codec id (a1, a0) read/write transfer description slot #0 bit 14 slot #0 bit 13 slot #0 bits 1 and 0 slot #1 bit 19 0 0 00 x idle no register data is transferred, slots 1 and 2 are not valid 1 x 00 1 primary read read for primary codec register 1 1 00 0 primary write write to a primary codec register x x 01 1 secondary read read from the 01 secondary codec register x x 11 0 secondary write write to a 11 secondary codec register
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 19 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 12.4 interrupt request from UCB1510 12.4.1 when bit_clk is running the aclink is active and the interrupt request is transmitted by setting the interrupt bit of slot 12 in the aclink frame. if UCB1510 is con?gured as a primary codec, this is the case when mlnk is set to 0. if UCB1510 is con?gured as a secondary codec, this is the case whether mlnk is set to 0 or 1. 12.4.2 when bit_clk is stopped in order to request an interrupt, the UCB1510 will assert the sdin pin, if mlnk is set to 1. bit_clk is not needed for this to happen. this applies when UCB1510 is used as a primary or secondary codec. if UCB1510 is con?gured as a primary codec, bit_clk is stopped as a result of mlnk being set to 1. if UCB1510 is con?gured as a secondary codec, bit_clk is stopped when the controller shuts down the primary codec. for UCB1510 to generate interrupt while bit_clk is stopped, mlnk has to be set to 1 before bit_clk is stopped. after bit_clk is stopped, sdin will be brought to 0, unless an interrupt asserts it to 1. it is recommended that a level triggered interrupt detection is used in case the interrupt request is asserted at the same time bit_clk is stopped. 12.5 wake-up request to the UCB1510 a cold reset will program the registers to their default value and will wake up the aclink. when the aclink is not active (no bit_clk present), a rising sync will cause a warm reset. if mlnk is set to 1, a rising reset will also cause a warm reset. after a warm reset, mlnk will be reset to 0. fig 9. setting the sdin for interrupt request mlnk bit_clk sdin interrupt request is enabled interrupt request
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 20 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 13. general purpose i/o the UCB1510 has 8 programmable digital input/output (i/o) pins. these pins can be independently programmed for polarity, value, direction and interrupt through the gpio control registers. 14. interrupt generation the UCB1510 contains a programmable interrupt control block. the internal interrupt signal presents the 'or' function of all interrupt status bits and can be used to give an interrupt to the system controller using the aclink interrupt protocol the interrupt controller is implemented asynchronously. this provides the possibility to generate interrupts when bit_clk is stopped, e.g. an interrupt can be generated in power down mode, when the state of one of the io pins changes (e.g. ring detect). 15. reset circuit and mode selection the ac97 speci?cation rev 2.1 describes a number of states and reset functions for a modem codec either in primary or secondary codec. 15.1 resets 15.1.1 pulling the pon pin low the pon pin acts as a hardware reset and is typically connected to a power detection circuit. 15.1.2 activating the reset pin pulling the reset pin low will start a cold or a warm reset sequence. if the circuit is active (mlnk = 0). a cold reset is started. the reset sequence will end after the rising edge of reset. only then will the aclink be available. vendor test modes are inactive as soon as the reset sequence starts so that mode sensing is possible. if the mlnk bit is set when the reset pin is pulled low, a warm reset is activated when reset goes high again. 15.1.3 activating the sync pin when aclink is inactive when the aclink is not active (no bit_clk present), a rising sync will cause a warm reset. 15.1.4 writing reg 0x3c when written, the reg 0x3c will initiate a register reset. all registers are set to their default values.
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 21 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 15.2 vendor test modes when starting a reset pin induced cold reset, the aclink pins are sensed for vendor test mode selection. bit_clk does not need to be running at that moment when the vendor test mode is activated, the vendor test register takes action. this mode is for test only and should not be used in normal operation. exiting this mode requires a cold reset. 15.3 primary/secondary codec selection secondary codec implementation is selected by wiring the a0 pin low. when a0 is low (a0 is 1), the xtal_in is used as a1 thus allowing 01 and 11 as secondary addresses. 10 is not possible. the id register will then re?ect the a1,a0. details can be found in the description of register 0x3c. when the UCB1510 is a secondary codec, it derives its internal clock from bit_clk. bitclk is therefore con?gured as input. 16. limiting values [1] stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the absolute maximum rating section of this speci?cation is not implied [2] parameters are valid over the ambient operating temperature unless otherwise speci?ed. all voltages are with respect to v ssd , unless otherwise noted. table 29: mode selection with ac pins sync sdout mode 0 0 normal mode, the aclink is operating properly. 0 1 ate test mode. all aclink pins are set to input thus allowing board level jtag testing. 1 0 vendor test mode. 1 1 ate test mode. table 30: limiting values in accordance with the absolute maximum rating system (iec 60134). [1] . [2] symbol parameter conditions min max unit v dd supply voltage - 0.5 +4.0 v v i dc input voltage - 0.5 v dd + 0.5 v v o dc output voltage - v dd + 0.5 v i i(d) diode input current - 10 ma i o(d) diode output current - 10 ma i o continuous output current, digital outputs - 4ma t stg storage temperature - 55 +150 c
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 22 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 17. thermal characteristics 18. static characteristics [1] indicative value measured during the initial characterization. table 31: thermal characteristics symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 55 k/w table 32: static characteristics v ssd =v ssa1 =0v; t amb =25 c; all voltages referenced to v ssd ; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ddd digital supply voltage 3.0 3.3 3.6 v v dda1 analog supply voltage 3.0 3.3 3.6 v i ddd digital supply current [1] - 19 - ma i dda1 digital supply current full functionality [1] -- ma i dda2 analog supply current power down, only oscillator is on t.b.d. v il low level input voltage - 0.5 - +0.2v ddd v v ih high level input voltage 0.8v ddd - 0.5v ddd v v ol low level output voltage i ol =4ma -- 0.4 v v oh high level output voltage i oh = 4 ma 0.8v ddd -- v f bit_clk serial interface clock frequency 12.288 mhz t amb operating ambient temperature - 20 - 70 c
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 23 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 19. dynamic characteristics table 33: dynamic characteristics v ssd =v ssa =0v; v ddd =v dda = 3.3 v 10%; t amb =25 c; v i(ref) = 1.2 v; f bit_clk = 12.288 mhz; unless otherwise speci?ed. symbol parameter conditions min typ max unit telecom input [1] f st sample frequency - 8 - khz v i(rms) input voltage (rms value) differentially applied to tinn and tinp; adc[3:2] = 1 (6 db) in register 0x46 330 370 410 mv v i(bias) dc bias voltage tinn/tinp 1.2 - 1.6 v a i input gain 0 6 18 db input gain step size 2 lsbs ignored, bit 3 step 468db z i input impedance 25 -- k w s/n signal-to-noise ratio 60 75 - db thd total harmonic distortion -- 75 - 60 db le (d)(adc) adc differential linearity error -- 2 lsb res codec resolution - 14 - bit pbrr pass-band ripple rejection f plt f st -- 25 mv z o(load) load impedance 600 --w e offset offset error [5] -- 100 mv
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 24 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. [1] additional test conditions: fsampl e = 8 khz; input signal 1 khz, 300 mv (rms); line1_adc_on = 1; tel_voice_ena = 0, input gain +6 db [2] additional test conditions: fsampling 8 khz; 0 db output attenuation; 90% of digital full scale input voltage; 1200 w load. [3] see figure 10 . [4] see figure 11 . [5] deviation of the analog output from 0, with 0 code input to telecom output path. [6] all curves repeat around the sample frequency f sa or f st for telecom codec. on-chip reference circuit v i(ref) reference voltage applied to vrefbyp 1.0 1.2 1.4 v t strtu start-up time of internal reference voltage circuit -- 1000 ns xtal oscillator f xtal operating frequency 12.288 mhz z xtal start-up time of internal reference voltage circuit 10 k w aclink control register data transfer f acclk clk input frequency 0 12.288 mhz d acclk clk duty factor - 50 - % reset circuit t w(nreset) reset pulse width 5 -- ns t w(rst) internal reset pulse width 32 t clk - ns table 33: dynamic characteristics continued v ssd =v ssa =0v; v ddd =v dda = 3.3 v 10%; t amb =25 c; v i(ref) = 1.2 v; f bit_clk = 12.288 mhz; unless otherwise speci?ed. symbol parameter conditions min typ max unit fig 10. telecom input frequency response f plt 0.0016 f st = f pht 0.42 f st = f sht 0.6 f st = f vlt 0.018 f st = f vht 0.05 f st = voice filter enabled 0db fpht pbrr sbrsht fplt fsht fvlt fvht sbrvti
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 25 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. fig 11. telecom output frequency response f plt 0.0016 f st = f pht 0.42 f st = f sht 0.6 f st = 0db sbr fplt fpht fsht frequency [hz] pbrr
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 26 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 20. package outline fig 12. ssop28 package; sot341-1. unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 27 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. 21. soldering 21.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations re?ow soldering is often used. 21.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 21.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured.
philips semiconductors UCB1510 ac97 digital modem codec preliminary speci?cation rev. 01 4 february 2000 28 of 32 9397 750 06856 ? philips electronics n.v. 2000. all rights reserved. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 21.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 21.5 package related soldering information [1] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [2] these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). [3] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [4] wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [5] wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 22. revision history table 34: suitability of surface mount ic packages for wave and re?ow soldering methods package soldering method wave re?ow [1] bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable [2] suitable plcc [3] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [3] [4] suitable ssop, tssop, vso not recommended [5] suitable table 35: revision history rev date cpcn description 01 991111 - converted to dbii format. the format of this speci?cation has been redesigned to comply with philips semiconductors new presentation and information standard.
philips semiconducto r s UCB1510 a c97 digital modem codec preliminary speci?cation r e v . 01 4 february 2000 29 of 3 2 9397 750 06856 ? philips electronics n. v . 2000 all r ights rese r v ed. d 23 . data sheet status [1] please consult the most recently issued data sheet be f ore initiating or completing a design. 24 . de?nitions sho r t- f orm speci?cation th e dat a i n a sho r t- f o r m speci?catio n is e xtracte d fro m a ful l dat a shee t wit h th e sam e typ e numbe r an d titl e . f or detailed in f o r mation see the rel e v ant data sheet or data handbook. limiting v alues de?nition limitin g v alue s gi v e n ar e i n accordanc e with th e absolut e maxi m u m ratin g syste m (ie c 60134) . stres s ab o v e on e or mor e o f th e limitin g v alue s m a y caus e pe r manen t damag e t o th e d e vic e . thes e ar e stres s rating s onl y an d ope r atio n o f th e d e vic e a t thes e o r a t a n y othe r condition s ab o v e thos e gi v e n i n th e characte r istic s section s o f the speci?catio n i s no t implied . exposur e t o limitin g v alue s f o r e xtende d pe r iods m a y af f ect d e vice reliabilit y . application in f ormation application s tha t ar e desc r ibe d herei n f o r a n y o f thes e product s ar e f o r illustrati v e pu r pose s onl y . philip s semiconductors ma k e n o representatio n o r w ar r ant y tha t suc h application s wil l b e suita b l e f o r the speci?ed use without fu r ther testing or modi?cation. 25 . dis c laime r s li f e suppo r t thes e product s ar e no t designe d f o r us e i n li f e suppo r t appliance s , d e vice s , o r system s wher e malfunctio n o f thes e product s can reasona b l y b e e xpecte d t o resul t i n persona l inju r y . philip s semiconductors customer s usin g o r sellin g thes e product s f o r us e i n suc h application s d o so a t thei r o w n r is k an d agre e t o full y indemnif y philip s semiconductor s f o r a n y damages resulting from such application. right to make chan g es philip s semiconductor s rese r v e s th e r igh t to ma k e change s , withou t notic e , i n th e product s , includin g circuit s , standard cell s , and/o r soft w ar e , desc r ibe d o r containe d herei n i n orde r t o impr o v e design and/or per f o r manc e . philips semiconductors assumes no responsibilit y o r liabilit y f o r th e us e o f a n y o f thes e product s , co n v e y s no licenc e o r titl e unde r a n y patent , co p y r ight , o r mas k wo r k r igh t t o these product s , an d ma k e s n o representation s o r w arrantie s tha t thes e products ar e fre e fro m patent , co p y r ight , o r mas k wo r k r igh t inf r ingement , unless otherwise speci?ed. datasheet status p r oduct status de?nition [1] objecti v e speci?cation d e v elopment this data sheet contains the design target or goal speci?cations f or product d e v elopment. speci?cation m a y change in a n y manner without notic e . prelimina r y speci?cation quali?cation this data sheet contains prelimina r y data, and supplementa r y data will be pu b lished at a later dat e . philips semiconductors rese r v es the r ight to ma k e changes at a n y time without notice in order to impr o v e design and supply the best possi b le product. product speci?cation production this data sheet contains ?nal speci?cation s . philips semiconductors rese r v es the r ight to ma k e changes at a n y time without notice in order to impr o v e design and supply the best possi b le product.
philips semiconducto r s UCB1510 a c97 digital modem codec preliminary speci?cation r e v . 01 4 february 2000 30 of 3 2 9397 750 06856 ? philips electronics n. v . 2000. all r ights rese r v ed. n o t e s
philips semiconducto r s UCB1510 a c97 digital modem codec preliminary speci?cation r e v . 01 4 february 2000 3 1 of 3 2 9397 750 06856 ? philips electronics n. v . 2000. all r ights rese r v ed. philips semiconductors - a worldwide company a r gentina: see south ame r ica a ustralia: t el . +6 1 2 970 4 8141 , f ax . +6 1 2 970 4 8139 a ustria: t el. +4 3 16 0 101, f ax . +4 3 16 0 10 1 1210 belarus: t el. +37 5 17 220 0733, f ax . +37 5 17 220 0773 belgium: see the nethe r lands brazil : see south ame r ica bulgaria: t el. +35 9 268 9211, f ax . +35 9 268 9102 canada: t el. + 1 80 0 23 4 7381 china/hong k ong: t el. +852 2 31 9 7888, f ax . +85 2 2 31 9 7700 colombia: see south ame r ica c z e c h republic: see a ust r ia denmark: t el. +4 5 3 28 8 2636, f ax . +4 5 3 15 7 0044 finland: t el. +35 8 96 1 5800, f ax . +35 8 9 6 15 8 0920 france: t el. +3 3 1 4 09 9 6161, f ax . +3 3 1 4 09 9 6427 germa n y: t el. +4 9 4 0 2 3 5360, f ax . +4 9 40 2 353 6300 hungary: see a ust r ia india: t el. +9 1 2 2 49 3 8541, f ax . +9 1 2 2 49 3 8722 indonesia: see singapore ireland: t el. +35 3 1 7 6 4 0000, f ax . +35 3 1 7 6 4 0200 israel: t el. +97 2 3 6 4 5 0444, f ax . +97 2 3 6 4 9 1007 ita l y: t el. +3 9 03 9 20 3 6838 , f ax +3 9 03 9 20 3 6800 japan: t el. +8 1 3 3 74 0 5130, f ax . +8 1 3 374 0 5057 k orea: t el. +8 2 2 7 0 9 1412, f ax . +8 2 2 7 0 9 1415 mal a ysia: t el. +60 3 7 5 0 5214, f ax . +6 0 3 7 5 7 4880 m e xico: t el. +9- 5 80 0 23 4 7381 middle east: see italy netherlands: t el. +3 1 4 0 27 8 2785, f ax . +3 1 4 0 27 8 8399 n e w zealand: t el. +6 4 9 8 4 9 4160, f ax . +6 4 9 8 4 9 7811 norw a y: t el. +4 7 2 2 7 4 8000, f ax . +4 7 2 2 7 4 8341 philippines: t el. +6 3 2 8 1 6 6380, f ax . +6 3 2 8 1 7 3474 p oland: t el. +4 8 2 2 571 0 000, f ax . +4 8 2 2 571 0 001 p o r tugal: see spain romania: see italy russia: t el. + 7 09 5 75 5 6918, f ax . + 7 09 5 75 5 6919 singapore: t el. +6 5 35 0 2538, f ax . +6 5 25 1 6500 sl ov akia: see a ust r ia sl o venia: see italy south africa: t el. +2 7 1 1 47 1 5401, f ax . +2 7 1 1 47 1 5398 south america: t el. +5 5 1 1 82 1 2333, f ax . +5 5 1 1 82 9 1849 spain: t el. +3 4 3 3 0 1 6312, f ax . +3 4 3 3 0 1 4107 sweden: t el. +4 6 8 6 3 2 2000, f ax . +4 6 8 6 3 2 2745 switzerland: t el. +4 1 1 4 8 8 2686, f ax . +4 1 1 4 8 1 7730 t aiwan: t el. +88 6 2 2 13 4 2865, f ax . +88 6 2 2 13 4 2874 thailand: t el. +6 6 2 7 4 5 4090, f ax . +6 6 2 3 9 8 0793 t urk e y: t el. +9 0 21 6 52 2 1500, f ax . +9 0 21 6 52 2 1813 ukraine: t el. +38 0 4 4 26 4 2776, f ax . +38 0 4 4 26 8 0461 united kingdom: t el. +4 4 20 8 73 0 5000, f ax . +4 4 20 8 75 4 8421 united states: t el. + 1 80 0 23 4 7381 urugu a y: see south ame r ica vietnam: see singapore y ugosl a via: t el. +38 1 1 1 6 2 5344, f ax . +38 1 1 1 6 3 5777 for all other countries app l y to: philips semiconductor s , inte r nationa l ma r k etin g & sale s com m unication s , buildin g be, p . o . b o x 218, 560 0 m d eindh o ven, th e nethe r land s , f ax . +3 1 4 0 27 2 4825 internet : http://ww w .semiconductor s .philip s .com (sca68)
? philips electronics n.v. 2000. printed in the u.s.a. al l right s ar e reserved . reproductio n i n whol e o r i n par t i s prohibite d withou t th e prior written consent of the copyright owner. th e informatio n presente d i n thi s documen t doe s no t for m par t o f an y quotatio n or contract , i s believe d t o b e accurat e an d reliabl e an d ma y b e change d withou t notice . no liabilit y wil l b e accepte d b y th e publishe r fo r an y consequenc e o f it s use . publication thereo f doe s no t conve y no r impl y an y licens e unde r patent - o r othe r industria l or intellectual property rights. date of release: 4 february 2000 document order number: 9397 750 06856 contents philips semiconducto r s UCB1510 a c97 digital modem codec 1 descriptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 application s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering informatio n . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning informatio n . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 5 8 telecom code c . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1 digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 analog interface . . . . . . . . . . . . . . . . . . . . . . . . 7 9 on-chip reference circuit . . . . . . . . . . . . . . . . . 8 10 power supply strateg y . . . . . . . . . . . . . . . . . . . . 8 11 register definitio n . . . . . . . . . . . . . . . . . . . . . . . 9 11.1 supported registers . . . . . . . . . . . . . . . . . . . . . 9 11.2 register detai l . . . . . . . . . . . . . . . . . . . . . . . . . . 9 11.2.1 extended modem i d . . . . . . . . . . . . . . . . . . . . . 9 11.2.2 extended modem status and contro l . . . . . . . 10 11.2.3 line 1 sample rate . . . . . . . . . . . . . . . . . . . . 10 11.2.4 line 1 dac/adc leve l . . . . . . . . . . . . . . . . . . 11 11.2.5 gpio pin configuration . . . . . . . . . . . . . . . . . 11 11.2.6 gpio pin polarity . . . . . . . . . . . . . . . . . . . . . . 11 11.2.7 gpio pin sticky . . . . . . . . . . . . . . . . . . . . . . . 12 11.2.8 gpio wake-up mask . . . . . . . . . . . . . . . . . . . 12 11.2.9 gpio pin statu s . . . . . . . . . . . . . . . . . . . . . . . 12 11.2.10 miscellaneous modem afe status and contro l 13 11.2.11 vendor specific codec contro l . . . . . . . . . . . . 14 11.2.12 vendor specific mode control . . . . . . . . . . . . 14 11.2.13 vendor specific test contro l . . . . . . . . . . . . . . 14 11.2.14 vendor id1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.2.15 vendor id2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.3 register reset modes . . . . . . . . . . . . . . . . . . . 15 11.3.1 warm rese t . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.3.2 cold rese t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.3.3 register rese t . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 ac97 interface . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.1 control register data transfer . . . . . . . . . . . . . 16 12.2 codec addressin g . . . . . . . . . . . . . . . . . . . . . . 18 12.2.1 primary codec addressing . . . . . . . . . . . . . . . 18 12.2.2 secondary codec addressin g . . . . . . . . . . . . . 18 12.3 pcm sample transfer . . . . . . . . . . . . . . . . . . . 18 12.4 interrupt request from ucb151 0 . . . . . . . . . . . 19 12.4.1 when bit_clk is running . . . . . . . . . . . . . . . 19 12.4.2 when bit_clk is stoppe d . . . . . . . . . . . . . . . 19 12.5 wake-up request to the UCB1510 . . . . . . . . . 19 13 general purpose i/ o . . . . . . . . . . . . . . . . . . . . . 20 14 interrupt generatio n . . . . . . . . . . . . . . . . . . . . . 20 15 reset circuit and mode selectio n . . . . . . . . . . 20 15.1 reset s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15.1.1 pulling the pon pin lo w . . . . . . . . . . . . . . . . 20 15.1.2 activating the reset pin . . . . . . . . . . . . . . . . 20 15.1.3 activating the sync pin when aclink is inactiv e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15.1.4 writing reg 0x3 c . . . . . . . . . . . . . . . . . . . . . . . 20 15.2 vendor test modes . . . . . . . . . . . . . . . . . . . . . 21 15.3 primary/secondary codec selection . . . . . . . . 21 16 limiting value s . . . . . . . . . . . . . . . . . . . . . . . . . 21 17 thermal characteristic s . . . . . . . . . . . . . . . . . . 22 18 static characteristic s . . . . . . . . . . . . . . . . . . . . 22 19 dynamic characteristics . . . . . . . . . . . . . . . . . 23 20 package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 21 solderin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 21.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 21.2 reflow solderin g . . . . . . . . . . . . . . . . . . . . . . . 27 21.3 wave solderin g . . . . . . . . . . . . . . . . . . . . . . . . 27 21.4 manual solderin g . . . . . . . . . . . . . . . . . . . . . . . 28 21.5 package related soldering information . . . . . . 28 22 revision histor y . . . . . . . . . . . . . . . . . . . . . . . . 28 23 data sheet statu s . . . . . . . . . . . . . . . . . . . . . . . 29 24 definition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 25 disclaimer s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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